A computer system is generally provided with an external storage for storing a large volume of data, which is typically a direct access storage device (DASD). When data is transferred between a host and the external storage in such a computer system, a buffer for speed adjustment is conventionally interposed there between since the host and external storage have different data transfer rates. For example, in a personal computer system, data transfer between a hard disk drive (HDD) used as a DASD and a host is performed through a buffer (usually called sector buffer) having the capacity of about 32K to 256K bytes. The sector buffer is physically provided on the side of the HDD and a hard disk controller (HDC) reads and writes the sector buffer under the control of a microprocessor.
In the past, a sector buffer stored only data to be transferred between a host and a disk, but a technique has been developed to access the sector buffer by a microprocessor controlling the entire HDD when the host-disk data transfer is not performed. For example, Japanese Published Unexamined Patent Application 2-51724 teaches that a path for connecting data and address buses from a microprocessor to a data buffer RAM is provided in a file data processor of a disk controller, in which the data buffer RAM is used not only as a data buffer at the time of disk access, but also for intelligent command processing for SCSI, for storing error handling programs therefor, and as a work area of the microprocessor. The microprocessor may access the data buffer RAM when a disk is not read or written. A program that allows the file data processor to read or write is stored in a read only memory (ROM) of the microprocessor.
It is also known that a host, one or more peripheral devices including a disk drive, and a microprocessor can all access a shared memory according to a predetermined priority. For example, U.S. Pat. No. 4,987,530 discloses a data processing system in which a single input/output controller including a microprocessor and a buffer memory controls a plurality of input/output devices through the respective input/output device controllers so that data transfer is performed between the input/output devices and a main memory of a host CPU through a local memory bus. The buffer memory stores not only data to be transferred through the local memory bus, but also microprocessor programs. An arbiter included in a buffer control gate array decides which device may access the buffer memory. Also Japanese Published Unexamined Patent Application 2-158824 discloses a similar storage controller using a shared memory. The shared memory is partitioned into a microprocessor data storage area, a disk data storage area, and a host data storage area each of which is selectively accessed according to a predetermined priority.
Operational sequences for data transfer through such a buffer were conventionally controlled by logic of a controller such as HDC or a microprocessor program. The former method using the hardware logic has a disadvantage of less extendibility and flexibility since the hardware is designed to fit a particular external storage to be controlled and, therefore, it should be redesigned if the external storage is changed. In case of the program control, the program may be merely rewritten when the external storage is changed, but a microprocessor can not do any other job during the data transfer, which requires microprocessor intervention all the time. Accordingly, a data transfer control system having the advantages of both prior systems is desired.